1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to the formation of a transistor utilizing a common chamber during the deposition of a gate dielectric upon a semiconductor topography followed by the deposition of a gate conductor layer upon the gate dielectric.
2. Description of the Relevant Art
Fabrication of a metal-oxide semiconductor ("MOS") transistor is well known in the art. The manufacture of an MOS transistor begins by defining active areas where the transistor will be formed. The active areas are isolated from other areas of the semiconductor topography by various isolation regions formed upon and within the topography. Isolation regions may be formed using various techniques. For example, the isolation regions can be formed by etching trenches into the topography and then filling the trenches with a dielectric fill material. Isolation regions may also be formed by locally oxidizing the silicon substrate using the well recognized local oxidation of silicon ("LOCOS") technique.
Once the isolation regions are defined between transistor active areas, a gate dielectric is formed. Typically, the gate dielectric is formed by thermal oxidation of the silicon substrate. Thermal oxidation is achieved by subjecting the substrate to an oxygen-bearing, heated ambient in an oxidation furnace or a rapid thermal anneal ("RTA") chamber. The gate conductor material is then deposited across the entire dielectric-covered substrate. The gate conductor material is preferably polycrystalline silicon, i.e., polysilicon. The polysilicon layer is then patterned using a photolithography mask. The mask allows select removal of a light-sensitive material deposited entirely across polysilicon. The material which is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed. Selective polymerization is often referred to as the "develop" stage of lithography. The regions which are non-polymerized are removed using the etch stage of lithography.
An n-channel transistor, or NMOS transistor, is in most instances fabricated differently from a p-channel transistor, or PMOS transistor. NMOS transistors employ n-type dopants on opposite sides of the NMOS gate conductor, whereas PMOS transistors employ p-type dopants on opposite sides of the PMOS transistor gate conductor. The regions of the substrate which receive dopants on opposite sides of the gate conductor are generally referred to as junction regions, and the distance between junction regions is typically referred to as the physical channel length.
A complementary MOS, or CMOS transistor, contains both NMOS and PMOS transistors upon a single, monolithic substrate. Only one type of these two transistors can be fabricated on a given doped substrate portion. Thus, a CMOS substrate can accommodate a substrate portion ("well") of opposite dopant than the initially doped substrate. Generally, wells are the first regions formed within the substrate of a CMOS integrated circuit. A well is formed via implantation and diffusion of an appropriate dopant within a defined area of the substrate. It is important to connect p-type wells to the most negative circuit voltage and n-type wells to the most positive circuit voltage. Since either an NMOS or PMOS device must be located in the well, there has been some differences as to which type of well to use in CMOS fabrication.
It is critical to maintain uniform and stable threshold voltages of MOS transistors. For example, having a stable threshold voltage V.sub.T is important in any semiconductor device. For example, a sense amplifier is a balanced flip-flop whose voltage-sensing capability is directly related to the threshold voltage variation between transistors within the amplifier. In CMOS circuits, it is desirable that the n- and p- channel devices have similar threshold magnitudes for optimal performance. Moreover, threshold voltages should be as small as possible in order for a CMOS circuit to have maximum current-driving capability. The minimum threshold voltage, however, needs to be at a value which prevents excessive subthreshold currents.
Polysilicon gate structures in CMOS devices are often doped to reduce their resistivities. It is ideal to use an n-type polysilicon gate for NMOS devices and a p-type polysilicon gate for PMOS devices in order to achieve low threshold voltages for both devices of a CMOS transistor. It is common to highly dope one gate conductor while covering the other gate conductor with a mask, thereby preventing the other gate conductor from becoming doped. Then the other gate conductor is doped at a lesser concentration than the initially doped gate conductor. The heavily doped gate conductor requires no mask during the doping of the other gate conductor since it bears a high concentration of one dopant and therefore cannot be effectively doped with another dopant. When a heavily doped polysilicon gate conductor is subjected to high temperature treatment, the dopants therein can migrate through the dielectric layer and into the oppositely doped channel. This allows the channel to be counterdoped by dopants from the gate conductor. This counterdoping can occur to the degree that the threshold voltage is deleteriously changed from its pre-designed value.
The gate dielectric in CMOS transistors is typically a thermally grown oxide. Since the drain current of the transistor is inversely proportional to the gate-oxide thickness, the gate oxide is normally made as thin as possible. In order to deposit polysilicon onto the gate oxide by CVD, the device is moved to a CVD chamber. Conventional CVD systems include the following components: gas sources; gas feed lines; mass-flow controllers for entering gases; a reaction chamber; a thermal energy source for heating wafers placed within the chamber; temperature sensors; and pumps for reducing chamber pressure and exhausting the gases from the chamber. Withdrawal of the oxide covered substrate from the CVD chamber allows native oxides or other impurities to grow or deposit upon the gate oxide. Contamination may produce charge trap locations in the gate oxide which can alter, for example, breakdown and threshold voltages of the device. Furthermore, the formation of a native oxide layer upon the gate oxide can negatively impact the source-to-drain current of the device.
It is therefore desirable to devise a CMOS device fabrication method in which the gate dielectric does not become exposed to ambient conditions before the deposition of polysilicon upon the gate dielectric. Prevention of exposure of the gate dielectric to ambient oxygen is beneficial in that the gate oxide remains at a controlled thickness with minimal contamination. Moreover, the desired method must be one which does not allow dopants within the gate conductor (normally heavy doped in a CMOS process flow) to migrate into the underlying channel. Such a method would help prevent threshold voltages skews from their favored values.